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ASAHI KASEI
[AK5380]
96kHz 24Bit ADC with Single-ended Input
GENERAL DESCRIPTION The AK5380 is a stereo A/D Converter with wide sampling rate of 4kHz96kHz and is suitable for Highend audio system. The AK5380 achieves high accuracy and low cost by using Enhanced dual bit techniques. The AK5380 requires no external components because the analog inputs are single-ended. The audio interface has two formats (MSB justified, I 2S) and can correspond to many systems like music instrument and AV receiver. FEATURES o Stereo ADC o On-Chip Digital Anti-Alias Filtering o Single-ended Input o Digital HPF for DC-Offset cancel o S/(N+D): 96dB@5V for 48kHz o DR: 106dB@5V for 48kHz o S/N: 106dB@5V for 48kHz o Sampling Rate Ranging from 4kHz to 96kHz o Master Clock: 256fs/384fs/512fs/768fs (48kHz) 256fs/384fs (96kHz) o Input level: TTL/CMOS selectable o Output format: 24bit MSB justified / I2S selectable o Power Supply: 4.55.5V (VA) 2.75.5V (VD at 48kHz) 4.55.5V (VD at 96kHz) o Ta=-4085C o Small 16pin TSSOP Package o AK5353 Pin-compatible
VA AGND VD DGND MCLK
AK5380
Clock Divider AINL Modulator Modulator Voltage Reference Decimation Filter Decimation Filter Serial I/O Interface
LRCK SCLK
AINR
SDTO
VCOM
TST
PDN
DIF
TTL
MS0100-E-01 -1-
2001/7
ASAHI KASEI
[AK5380]
n Ordering Guide
AK5380VT AKD5380 -40+85C Evaluation Board 16pin TSSOP
n Pin Layout
AINR AINL NC VCOM AGND VA VD DGND
1 2 3 4 5 6 7 8
16 15 14
TST TTL DIF PDN SCLK MCLK LRCK SDTO
Top View
13 12 11 10 9
n The difference with AK5353
AK5353 84dB 96dB 2.7 to 5.5V 60k(@48kHz) VREF pin AK5380 96dB 106dB 4.5 to 5.5V 15k(@48kHz) NC pin
S/(N+D) DR,S/N VA(Analog Supply) Input Resistance Pin #3
MS0100-E-01 -2-
2001/7
ASAHI KASEI
[AK5380]
PIN/FUNCTION
No. 1 2 3 4 Pin Name AINR AINL NC VCOM I/O I I O Description Rch Analog Input Pin Lch Analog Input Pin NC Pin No internal bonding. Common Voltage Output Pin Normally connected to AGND with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 2.2F. Analog Ground Pin, 0V Analog Power Supply Pin, +4.5+5.5V Digital Power Supply Pin, +2.7+5.5V(fs=48kHz), +4.5+5.5V(fs=96kHz) Digital Ground Pin, 0V Serial Data Output Pin Data bits are presented MSB first, in 2's complement format. This pin is "L" in the power-down mode. Left/Right Channel Select Pin The fs clock is input to this pin. Master Clock Input Pin Serial Data Input Pin Output data is clocked out on the falling edge of SCLK. Power-Down Pin When "L", the circuit is in power-down mode. The AK5380 should always be reset upon power-up. Serial Interface Format Pin "L": MSB justified, "H": I2S Digital Input Level Select Pin "L": CMOS level (VD=2.75.5V), "H": TTL level (VD=4.55.5V) Test Pin (Internal pull-down pin) This pin should be left open.
5 6 7 8 9
AGND VA VD DGND SDTO
O
10 11 12 13
LRCK MCLK SCLK PDN
I I I I
14 15 16
DIF TTL TST
I I I
Note: All input pins except pull-down pins should not be left floating.
MS0100-E-01 -3-
2001/7
ASAHI KASEI
[AK5380]
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1) Parameter Power Supplies Analog (VA pin) Digital (VD pin) |AGND-DGND| Input Current (any pins except for supplies) Analog Input Voltage (AINL, AINR pins) Digital Input Voltage Ambient Temperature Storage Temperature Symbol VA VD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 85 150 Units V V V mA V V C C
Notes: 1. All voltages with respect to ground. 2. AGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital (fs=4kHz to 48kHz) Digital (fs=4kHz to 96kHz) Symbol VA VD VD min 4.5 2.7 4.5 typ 5.0 5.0 5.0 max 5.5 VA VA Units V V V
Notes: 1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0100-E-01 -4-
2001/7
ASAHI KASEI
[AK5380]
ANALOG CHARACTERISTICS
(Ta=25C; VA,VD=5V; fs=48kHz; I/F format=Mode 0; Signal Frequency =1kHz; Measurement band width=20Hz20kHz; BW=40Hz40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max ADC Analog Input Characteristics: Resolution 24 S/(N+D) (-1dBFS) (Note 4) fs=48kHz 88 96 fs=96kHz 82 90 DR (-60dBFS) (Note 5) fs=48kHz, A-weighted 100 106 fs=96kHz 94 102 S/N fs=48kHz, A-weighted 100 106 fs=96kHz 94 102 Interchannel Isolation 90 110 DC Accuracy Interchannel Gain Mismatch 0.1 0.5 Gain Drift 100 150 Input Voltage (Note 6) fs=48kHz 2.8 3.0 3.2 fs=96kHz 3.0 3.2 3.4 Input Resistance (Note 7) 10 15 Power Supply Rejection (Note 8) 50 Power Supplies Power Supply Current (VA+VD) Normal Operation (PDN= "H", fs=48kHz) (Note 9) 24 36 Normal Operation (PDN= "H", fs=96kHz) (Note 9) 30 45 Power-Down Mode (PDN= "L") 10 100
Units Bits dB dB dB dB dB dB dB dB ppm/C Vpp Vpp k dB
mA mA A
Notes: 4. The ratio of the rms value of the signal to the rms sum of all the spectral components less than 20kHz bandwidth, including distortion components. 5. S/(N+D) which is measured with an input signal of -60dB below full-scale. 6. This value is the full scale(0dB) of the input voltage. Input voltage is proportional to VA. (Vin=0.6xVA) 7. 9k(typ) and 6k(min) at fs=96kHz. 8. PSR is applied to VA,VD with 1kHz, 50mVpp. 9. VA=16mA(typ); VD=8mA(typ)@48kHz&5V, 5mA(typ)@48kHz&3V, 14mA(typ)@96kHz&5V.
MS0100-E-01 -5-
2001/7
ASAHI KASEI
[AK5380]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25C; VA=4.55.5V; VD=2.75.5V; fs=48kHz) Parameter Symbol Digital Filter (Decimation LPF) Passband (Note 10) -0.005dB PB -0.02dB -0.06dB -6.0dB Stopband (Note 10) SB Stopband Attenuation SA Group Delay Distortion GD Group Delay (Note 11) GD Digital Filter (HPF) Frequency Response: -3dB FR -0.5dB -0.1dB min 0 26.5 80 typ max 21.5 Units kHz kHz kHz kHz kHz dB s 1/fs Hz Hz Hz
21.768 22.0 24.0
0 27.6 1.0 2.9 6.5
-
Notes: 10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC.
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25C; VA=4.55.5V; VD=4.55.5V; fs=96kHz) Parameter Symbol Digital Filter (Decimation LPF) Passband (Note 10) -0.005dB PB -0.02dB -0.06dB -6.0dB Stopband (Note 10) SB Stopband Attenuation SA Group Delay Distortion GD Group Delay (Note 11) GD Digital Filter (HPF) Frequency Response: -3dB FR -0.5dB -0.1dB min 0 53.0 80 typ max 43.0 Units kHz kHz kHz kHz kHz dB s 1/fs Hz Hz Hz
43.536 44.0 48.0
0 27.6 2 5.8 13
-
Notes: 10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC.
MS0100-E-01 -6-
2001/7
ASAHI KASEI
[AK5380]
DIGITAL CHARACTERISTICS (CMOS level input)
(Ta=25C; VA=4.55.5V; VD=2.75.5V; TTL = "L") Parameter Symbol High-Level input voltage VIH Low-Level input voltage VIL VOH High-Level output voltage (Iout= -100A) VOL Low-Level output voltage (Iout= 100A) Input leakage current (except TST pin) Iin min 0.7xVD VD-0.5 typ Max 0.3xVD 0.5 10 Units V V V V A
DIGITAL CHARACTERISTICS (TTL level input)
(Ta=25C; VA=4.55.5V; VD=4.55.5V; TTL = "H") Parameter Symbol High-Level input voltage (TTL pin) VIH (All pins except TTL pin) VIH Low-Level input voltage (TTL pin) VIL (All pins except TTL pin) VIL VOH High-Level output voltage (Iout= -100A) VOL Low-Level output voltage (Iout= 100A) Input leakage current (except TST pin) Iin min 0.7xVD 2.2 VD-0.5 typ Max 0.3xVD 0.8 0.5 10 Units V V V V V V A
MS0100-E-01 -7-
2001/7
ASAHI KASEI
[AK5380]
SWITCHING CHARACTERISTICS (fs=4kHz48kHz)
(Ta=-4085C; VA=4.55.5V; VD=2.75.5V; CL=20pF) Parameter Symbol Control Clock Frequency Master Clock 256fs: fCLK Pulse Width Low tCLKL Pulse Width High tCLKH 384fs: fCLK Pulse Width Low tCLKL Pulse Width High tCLKH 512fs: fCLK Pulse Width Low tCLKL Pulse Width High tCLKH 768fs: fCLK Pulse Width Low tCLKL Pulse Width High tCLKH SCLK Frequency fSLK LRCK Frequency fs Serial Interface Timing (Note 12) tSLK SCLK Period tSLKL SCLK Pulse Width Low tSLKH Pulse Width High tLRSH LRCK Edge to SCLK "" (Note 13) tSHLR SCLK "" to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK "" to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW tPDV PDN "" to SDTO delay (Note 15) min 1.024 32 32 1.536 21 21 2.048 16 16 3.072 11 11 4 160 65 65 30 30 35 35 150 4129 typ max 12.288 Units MHz ns ns MHz ns ns MHz ns ns MHz ns ns MHz kHz ns ns ns ns ns ns ns ns 1/fs
18.432
24.576
36.864
6.144 48
Notes: 12. Refer to the operating overview section "Serial Data Interface". 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN rising.
MS0100-E-01 -8-
2001/7
ASAHI KASEI
[AK5380]
SWITCHING CHARACTERISTICS (fs=48kHz96kHz)
(Ta=-4085C; VA=4.55.5V; VD=4.55.5V; CL=20pF) Parameter Symbol Control Clock Frequency Master Clock 256fs: fCLK Pulse Width Low tCLKL Pulse Width High tCLKH 384fs: fCLK Pulse Width Low fCLKL Pulse Width High fCLKH SCLK Frequency fSLK LRCK Frequency fs Serial Interface Timing (Note 12) tSLK SCLK Period tSLKL SCLK Pulse Width Low tSLKH Pulse Width High tLRSH LRCK Edge to SCLK "" (Note 13) tSHLR SCLK "" to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK "" to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW tPDV PDN "" to SDTO delay (Note 15) min 12.288 16 16 18.432 11 11 48 160 65 65 30 30 20 20 150 4129 typ max 24.576 Units MHz ns ns MHz ns ns MHz kHz ns ns ns ns ns ns ns ns 1/fs
36.864
6.144 96
Notes: 12. Refer to the operating overview section "Serial Data Interface". 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN rising.
MS0100-E-01 -9-
2001/7
ASAHI KASEI
[AK5380]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs
VIH
LRCK
VIL
tSLK
VIH
SCLK tSLKH tSLKL
VIL
Clock Timing
VIH VIL tSHLR tLRSH VIH VIL tDLR tDSS
LRCK
SCLK
SDTO
50%VD
Serial Interface Timing
tPDW VIH VIL tPWV
PDN
SDTO
50%VD
Power-down & Reset Timing
MS0100-E-01 - 10 -
2001/7
ASAHI KASEI
[AK5380]
OPERATION OVERVIEW n System Clock Input
The external clocks which are required to operate the AK5380 are MCLK(256fs/384fs/512fs/768fs), LRCK(1fs), SCLK. MCLK should be synchronized with LRCK but the phase is not critical. When 384fs, 512fs or 768fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x 1/2=768fs x 1/3). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK5380. All external clocks (MCLK,BICK,LRCK) should always be present whenever the AK5380 is in normal operation mode (PDN = "H"). If these clocks are not provided, the AK5380 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5380 should be in the power-down mode (PDN = "L"). After exiting reset at power-up etc., the AK5380 is in the power-down mode until MCLK and LRCK are input. fs 32.0kHz 44.1kHz 48.0kHz 96.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz 24.5760MHz MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A SCLK 64fs 128fs 2.0480MHz 4.0960MHz 2.8224MHz 5.6448MHz 3.0720MHz 6.1440MHz 6.1440MHz N/A
768fs 24.576MHz 33.8688MHz 36.8640MHz N/A
Table 1. Example of System Clock
n Serial Data Interface
Two kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding to the setting of DIF pin. The format of output data is 2's complement MSB first. Mode 0 1 DIF 0 1 Format 24bit, MSB justified, L/R, SCLK 48fs (16bit, MSB justified, L/R, SCLK=32fs) 24bit, I2S, SCLK 48fs (16bit, I2S, SCLK=32fs) Table 2. Audio Serial Interface Formats
MS0100-E-01 - 11 -
2001/7
ASAHI KASEI
[AK5380]
LRCK
0 1 2 22 23 24 25 31 0 1 2 22 23 24 25 31 0 1
SCLK (64fs) SDTO
23 22 21 23:MSB, 0:LSB 1 0 23 22 21 23:MSB, 0:LSB 1 0 23 22
Lch Data Figure 1. Mode 0 Timing (SCLK=64fs) LRCK
0 1 2 3 11 12 13 14 15 0 1 2 3
Rch Data
11
12
13
14
15
0
1
SCLK (32fs) SDTO
15 14 13 12 15:MSB, 0:LSB 4 3 2 1 0 15 14 13 12 15:MSB, 0:LSB 4 3 2 1 0 15 14
Lch Data Figure 2. Mode 0 Timing (SCLK=32fs) LRCK
0 1 2 22 23 24 25 31 0 1 2
Rch Data
22
23
24
25
31
0
1
SCLK (64fs) SDTO
23 22 2 1 0 23 22 2 1 0 23
23:MSB, 0:LSB
23:MSB, 0:LSB
Lch Data Figure 3. Mode 1 Timing (SCLK=64fs) LRCK
0 1 2 3 4 12 13 14 15 0 1 2 3 4
Rch Data
12
13
14
15
0
1
SCLK (32fs) SDTO
0 15 14 13 12 15:MSB, 0:LSB 4 3 2 1 0 15 14 13 12 15:MSB, 0:LSB 4 3 2 1 0 15
Lch Data Figure 4. Mode 1 Timing (SCLK=32fs)
Rch Data
MS0100-E-01 - 12 -
2001/7
ASAHI KASEI
[AK5380]
n Power down
The AK5380 is placed in the power-down mode by bringing PDN "L" and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2's complement "0". The ADC outputs settle in the data corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).
4129/fs(86.021ms@fs=48kHz)
PDN Internal State A/D In (Analog) A/D Out (Digital) Clock In
MCLK,LRCK,SCLK
Normal Operation GD (1)
Power-down
Initialize
Normal Operation GD
Idle Noise
(2) "0"data
"0"data
Idle Noise
(3)
Notes: (1) Digital output corresponding to analog input has the group delay (GD). (2) A/D output is "0" data at the power-down state. (3) When the external clocks (MCLK,SCLK,LRCK) are stopped, the AK5380 should be in the power-down state. Figure 5. Power-down/up sequence example
n System Reset
The AK5380 should be reset once by bringing PDN "L" after power-up. The internal timing starts clocking by the rising edge (falling edge at mode1) of LRCK after exiting from reset and power down state by MCLK.
MS0100-E-01 - 13 -
2001/7
ASAHI KASEI
[AK5380]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
10u
Rch In Lch In
+ 10u + 2.2u + 10u + 0.1u 0.1u
1 2 3 4 5
AINR AINL NC VCOM AGND Top View VA VD DGND
TST 16 TTL 15
Mode Control Power-down Control
AK5380
DIF 14 PDN 13 SCLK 12 MCLK 11 LRCK 10 SDTO 9
Analog 5V
6 7
0.1u
Controller
10u +
8
Analog Ground
System Ground
Figure 6. Typical Connection Diagram Note: The value of electrolytic capacitor at VCOM depends on the low-frequency noise of power supply.
Digital Ground
Analog Ground
1
AINR AINL NC VCOM AGND VA VD DGND
TST 16 TTL 15 DIF 14
System Controller
2 3 4 5 6 7 8
AK5380
PDN 13 SCLK 12 MCLK 11 LRCK 10 SDTO 9
Figure 7. Ground Layout Note: AGND and DGND must be connected to the same analog ground plane.
MS0100-E-01 - 14 -
2001/7
ASAHI KASEI
[AK5380]
1. Grounding and Power Supply decoupling The AK5380 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5380 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5380 as possible, with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1F ceramic capacitor. An electrolytic capacitor 2.2F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5380. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 15k(typ)@fs=48kHz resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp(typ)@fs=48kHz. The ADC output data format is 2's complement. The DC offset is removed by the internal HPF. The AK5380 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5380 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
MS0100-E-01 - 15 -
2001/7
ASAHI KASEI
[AK5380]
PACKAGE
16pin TSSOP (Unit: mm)
5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 0.10 010
Epoxy Cu Solder plate 2001/7 - 16 -
1 0.220.1
8 0.65
Seating Plane
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0100-E-01
4.4
ASAHI KASEI
[AK5380]
MARKING
AKM 5380VT XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 5380VT Asahi Kasei Logo
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0100-E-01 - 17 -
2001/7

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